Hi, I’m Claire Jeongeun Kim, currently a Ph.D. student at University of Southern California. 🐎✌️ I’m grateful to be advised by Professor Christopher Torng and to be a member of Acorn Research Group 🐿️. My research interests are in the area of computer architecture, VLSI and fundamental abstractions for agile chip development methodologies.

During my master’s studies, I was advised by Professor Seung Eun Lee.
For more information about the lab, please visit the Computer Architecture Lab and my personal page.

📃 For further details, please find my CV (as of Dec 2025)

Experience

🐿️ [Aug, 2023 - Present] USC, Acorn Research Group, Research Assistant
💼 [Jan, 2023 - Jul, 2023] Korea Electronics Technology Institute(KETI), Researcher
📔 [Jan, 2021 - Feb, 2023] Seoultech, Computer Architecture Lab, Research Assistant
💼 [Jan, 2017 - Jan, 2021] SEMES, Hardware Design Engineer
📔 [Jan, 2014 - Feb, 2017] Seoultech, Intelligent Control Lab, Undergraduate Researcher

Education

👩‍💻 2023-Present Ph.D. in Electrical and Computer Engineering, USC
🎓 2021-2023 M.S. in Electronic Engineering, Seoultech
• Thesis: Parallel stochastic computing architecture for computationally intensive applications
🎓 2013-2017 B.S. in Electronic Engineering, Seoultech

Honors & Awards

2023 USC Graduate School Fellowship
2022 The 23rd Semiconductor Design Competition of Korea Corporate Special Award
• Korea Semiconductor Industry Association
• Topic: AI Processor employing Stochastic Computing for Embedded Systems
• [Slides] [Photo from the competition] [News]

Skills

• Hardware description language: Verilog, System Verilog, VHDL
• High-level Computer Language: C/C++, Python
• EDA tools: Design Compiler, Innovus, Genus, IC Compiler, IC Compiler II, PrimeTime, VCS, Verdi, Formality, StarRC, Quartus II, ModelSim, PSpice, Altium, Virtuoso

Graduate courses

[USC]
EE457 – Computer Systems Organization
• CPU architecture, pipelining, caches, virtual memory, Tomasulo OoO, CMP & coherency
• Designed CPU, ALU, FIFO, and branch logic in Verilog

EE477 – MOS VLSI Circuit Design
• CMOS logic, device modeling, interconnects, static/dynamic circuits
• Designed full adder, multiplier, divider, and DFF schematic/layout in Virtuoso

EE560 – Digital System Design
• Gated clocking, non-linear pipelines, Tomasulo OOO engine, CMP, PCIe, GPGPU, DRAM/DDR
• Implemented cache, CPU, FIFO (BRAM), Tomasulo units (FRL, BPB, SAB, SB, CFC, IU, ROB, Dispatch), AXI, CMP, PCIe, GPGPU modules in VHDL

EE577a – VLSI System Design
• Logical effort, pipelining, SRAM/CAM/DRAM
• Designed 512-bit SRAM (sense amp, precharge, decoders, write driver, output register) in Virtuoso

EE577b – VLSI System Design II
• On-chip networks, IO, DFX methodologies
• Built and verified a 4×4 mesh NoC with CPU nodes in SystemVerilog

EE599 – Complex Digital ASIC System Design
• Synthesis, timing constraints, CTS, P&R, power domains
• Integrated top-level ASIC design and on-chip clock generator using Intel 16nm technology

EE658 – Diagnosis and Design of Reliable Digital Systems
• Fault simulation, ATPG, boundary scan, BIST, memory/delay testing
• Developed logic & fault simulator and ATPG (D-algorithm, PODEM) in C++

CSCI570 – Analysis of Algorithms
• Greedy, divide-and-conquer, dynamic programming, network flow, NP-completeness, linear programming
• Implemented sequence alignment algorithms (basic & memory-efficient) in Python

[Seoultech]
9530036 Resilient Processor Design,
9530061 AI Processor Architecture,
9530034 SoC Design Methodology,
9530040 Advanced Computer Architecture,
9530055 Pattern Recognition,
9520073 Introduction to integrated circuits and systems,
9520063 RF/Analog Integrated Circuits and Systems,
9530016 Solid State Theory

Updates

• Dec 2024 Passed the PhD screening exam with EE457, EE477, EE577a, EE658, CSCI570!